The present invention relates to an improvement in a data extracting circuit for extracting a digital signal of rectangular waveform digitally modulated, for example, so that a D.C. component becomes substantially zero and recorded on a recording medium by reproducing, as an analog signal via a pickup, the digital signal and identifying high and low levels from the reproduced signal.
Recently, a digital modulation system for digitally modulating an analog signal to reduce the D.C. component to substantially zero has been developed owing to the advances made in PCM recording and reproducing techniques. A design for suppressing the D.C. component of the output signal of a data extracting circuit has also been carried out in which a recording signal is reproduced as an analog signal from the recording medium such as a magnetic tape, an optical disc or the like, on which digitally modulated data is recorded in such a modulation system and digital data of high and low levels are identified and reproduced from the reproduced analog signal.
FIG. 1 shows a conventional data extracting circuit for a modulation signal in which a D.C. component is suppressed to zero or to a very low value. More particularly, a signal S.sub.HF read out via a magnetic head or an optical pickup (not shown) from a recording medium is amplified through an input terminal IN by a preamplifier 11 and is supplied as a signal S.sub.A to a waveform equalizer 12. Since this signal S.sub.A is distorted in the waveform by a noise, an interference between codes, jitter and the like, the signal is corrected by the equalizer 12 in the reproduced waveform. The signal S.sub.EQ thus corrected in the waveform is formed to a signal S.sub.AGC of constant level by an AGC amplifier 13A which consists of a voltage variable gain amplifier 13, a level detector 14 for detecting the output level of the amplifier 13, and an error amplifier 15 for comparing the output of the detector 14 with a STD voltage for setting a level and generating a control voltage for controlling the gain of the amplifier 13 so as to always attain the set level. The signal S.sub.AGC is compressed in its amplitude by a limiter amplifier 16 which is constructed to vary the bias point of the signal S.sub.AGC by varying the D.C. voltage V.sub.a at the point a, and consists of a capacitor C.sub.1, resistors R.sub.1 to R.sub.4, diodes D.sub.1, D.sub.2 and an operational amplifier A.sub.1. The compressed level becomes 2V.sub.F at the peak-to-peak, where the forward voltages of the diodes D.sub.1, D.sub.2 are V.sub.F. The output signal S.sub.CLMP of the amplifier 16 is shaped into a waveform by a comparator 17 and led as binary extracted data S.sub.D identified at the high and low levels to an output terminal OUT and produced as a D.C. voltage V.sub.b through a low pass filter 18 which consists of a resistor R.sub.5, a capacitor C.sub.2 and a resistor R.sub.6, a capacitor C.sub.3. The D.C. voltage V.sub.b indicates the D.C. component of the reproduced modulated signal of the extracted data, and when the voltage V.sub.b is zero, the extracted binary data S.sub.D is obtained. When the voltage V.sub.b is positive, the bias voltage of the output signal S.sub.O of the amplifier A.sub.1 is shifted to the negative direction from the present state by enhancing the positive direction of the bias voltage V.sub.a of the amplifier A.sub.1.
Conversely, when the voltage V.sub.b is negative, the bias voltage of the output signal S.sub.O of the amplifier A.sub.1 is shifted toward the positive from the present state by lowering the bias voltage V.sub.a of the amplifier A.sub.1 from the present state toward the negative direction. The integrated result of the signal S.sub.CLMP compressed in the amplitude of .+-.V.sub.F is always zero in the above-described operation, the binary data S.sub.D shaped into a waveform by the comparator 17 coincides with the modulating regulation, and is outputted through a terminal OUT to a demodulator (not shown). A circuit for generating the optimum bias voltage by varying the bias voltage V.sub.a of the amplifier A.sub.1 in response to the variation in the D.C. voltage V.sub.b as described above consists of an error (D.C.) amplifier 19 having resistors R.sub.7, R.sub.8 and an operational amplifier A.sub.2, a STD voltage regulating circuit 20 having resistors R.sub.9, R.sub.10, and a variable resistor VR.sub.1. In other words, the bias voltage V.sub. a is varied by a closed loop control system having the amplifier 16, the low pass filter 18 and an error amplifier 19 which follow the displacement of the modulating regulation.
FIG. 2 shows a graphical diagram illustrating the signals S.sub.I, S.sub.O, S.sub.CLMP, S.sub.D in waveforms of the units in FIG. 1. V.sub.0 in FIG. 2 shows the bias level of the output terminal of the amplifier A.sub.1.
Specifically, the extracted data S.sub.D which coincides with the modulating regulation can be obtained by setting the level for identifying the amplitudes of high and low levels in the eye pattern of the input signal S.sub.I (such as a recorded and reproduced signal or received signal of the digitally modulated signal in which the D.C. component becomes zero as shown in FIG. 3) to the center of the amplitude of the component wave (which is called "eye center") having a time slot corresponding to the minimum inverting interval T.sub.min. In this case, the eye center does not always coincide with the center of the entire amplitude of the input signal S.sub.I as shown in FIG. 3, waveform (a) which relates the recording state to the recording medium, but becomes high level as shown in FIG. 3, waveform (b) or low level as shown in FIG. 3, waveform (c). Even in this case, it is, of course, necessary to always move the identification level of the high and low levels up to the central level of the eye.
However, in the above-described conventional data extracting circuit, because the integrated value V.sub.b of the output signal S.sub.CLMP of the amplifier 16 does not always coincide with the modulation regulation in the state of V.sub.b =0 due to the imbalance of the amplitude compressing characteristics caused by the irregular output offset voltage of the amplifier A.sub.1 and forward voltage characteristics of the amplitude compressing diodes D.sub.1, D.sub.2 in the amplifier 16, and the standard voltage of the amplifier 19 which cannot be fixed at zero, it is necessary to provide a standard voltage regulator 20 which employs a variable resistor VR.sub.1. Further, the large displacement from the set value of the standard voltage introduces increases in the error rate due to the mismatch of the extracted binary data S.sub.D to the modulation regulation, and it is necessary to provide the standard voltage regulator 20 as a circuit which is only marginally affected by the influence of the variation in the temperature and moisture, the variation in the voltage of a standard voltage source or a vibration, which creates complicated a circuit configuration that is expensive.